The field of the present invention is electronic circuits for frequency synthesis. More particularly, the present invention relates to a prescaler electronic circuit which uses a swallow counter.
Wireless communication systems transmit and receive modulated radio frequency (RF) signals, generally in accord with one or more telecommunications standard. These telecommunication standards, such as GSM, CDMA, CDMA2000, PDC, PHS, and others, generally set out specific and narrow bands of frequency operation. In order to maintain compliance with the frequency standards, wireless transceivers may use a crystal controlled oscillator to provide a highly accurate and stable frequency source, which controls and maintains the frequency output of a higher frequency local oscillator. Although the crystal controlled oscillator is a very good frequency source, it may take considerable time for the crystal oscillator to settle to a stable condition. In this regard, it is relatively time consuming to change the output frequency by adjusting the reference frequency. Since the wireless device may often need to change channels, and therefore frequency, it is undesirable to change the crystal oscillator and wait for the crystal oscillator to settle for each change. Further, the desired frequency change is often relatively small so alternatives to adjusting the crystal oscillator are often used.
In one method that avoids frequent changes to the crystal oscillator, a programmable divider circuit may be used to divide the local oscillator signal to a desired lower frequency. Using the selected divide ratio, the local oscillator signal is divided to a lower frequency, which is then locked to the reference signal from the crystal controlled oscillator. If there is a difference in frequency between the reference signal and the divided signal, then a feedback loop is used to appropriately adjust the frequency of the local oscillator. In this way, the local oscillator frequency is adjusted according to the divide ratio used in the programmable divider. In another use, the divide ratio of the programmable divider may be changed to generate different signal frequencies. In this way, different lower frequency signals may be readily available for use.
Programmable divider circuits may have frequency limitations, so if higher frequencies are used, a prescaler circuit may be used. A prescaler may divide at a fixed ratio, or for more flexibility, may allow for dividing at one of two available divide ratios. A prescaler with two available divide ratios or modes is often referred to as a dual modulus prescaler. The dual modulus prescaler has a mode control that allows a control circuit to set a first mode where the prescaler divides by a first divide ratio, or set a second mode where the prescaler divides by a second divide ratio. Since the prescaler usually operates at the frequency of the local oscillator signal, the prescaler circuit is typically kept compact and efficient. Accordingly, the dual modulus prescaler usually provides for only low order division. For example, a common dual modulus prescaler permits either dividing by 4 or dividing by 5. Since the local oscillator signal's frequency may be very high, for example, over 1 GHz, dividing by 4 or 5 does not sufficiently reduce the frequency for many wireless devices, and the frequency resolution may be too great to comply with the narrow channel separations in some of the telecommunications standards. For example, the local oscillator signal may need to be divided to operate near the frequency output of a crystal controlled oscillator.
To increase resolution and to offer more frequency reduction, the prescaler is often coupled to an extender circuit. The extender circuit is often a simple divide circuit that further divides the output from the prescaler. For example, a divide-by-8 extender may be connected to the 4/5 prescaler, with the resulting combined circuit acting as a dual 32/33 circuit. Although the dual 32/33 circuit provides adequate frequency reduction and frequency resolution for many wireless devices, it is difficult to satisfactorily implement. For example, a typical dual 32/33 circuit is often plagued by a dead zone. The dead zone is a window of time when the 4/5 prescaler may not properly respond to a mode command to change its divide ratio. If the mode command is generated during the dead zone, the low-order 4/5 prescaler will fail to properly transition to the second divide ratio. Missing the mode command results in an output signal that may jitter, have glitches, or cause a frequency drift, which is highly undesirable in sensitive radio devices. Although the dead zone is described with reference to the 32/33 combined circuit, other combinations may also have a similar dead zone problem.
The dead zone is a result of timing errors and delays inherent in the combination and supporting circuitry. These timing errors and delays are likely to be sensitive to temperature and process variations, so the impact of the dead zone will also vary between devices, and may change with temperature and age. Since the circuitry may be subject to such variation, it is particularly difficult to implement a design that can reliably avoid the dead zone. To minimize the undesirable effects of the dead zone, the combination circuitry may be designed with a relatively large margin of error for timing relationships, thereby increasing circuit cost and complexity. Also, signals may be processed to keep cleaner pulse shapes, which may result in fewer timing ambiguities. However, operating the 32/33 circuit with such pulses may use more power, generate more heat, and require higher quality circuitry and complex designs.
Therefore, there exists a need for a frequency prescaler that provides adequate frequency reduction, required frequency resolution, and that can be efficiently and robustly implemented.